1. Field of the Invention
This invention relates to the field of differential transistor amplifier stages, and particularly to circuits and methods for trimming a differential transistor stage's offset voltage.
2. Description of the Related Art
All transistor amplifiers are prone to voltage offset (Vos) errors which affect their accuracy. Offset error contributions to a MOSFET amplifier originate via several mechanisms. The most common cause of offset error in a MOSFET input stage arises due to a mismatch between the threshold voltages (VT) of the two transistors making up the differential input pair. Several schemes are known to trim out this error. Often, a trim current will be injected differentially into the drains of the input pair; this approach is shown in FIG. 1a. A differential input pair MN1 and MN2 have their source terminals connected to a common node 10, and their gates connected to receive a differential input voltage V+−V−. A bias current source 12 provides a bias current to common node 10 such that MN1 and MN2 conduct respective output currents in response to a differential input voltage applied to V+ and V−; here, the input stage drives an active load comprising transistors MP1 and MP2. Trim currents sources 14 and 16 inject trim currents Itrim+ and Itrim− into the drains of MN1 and MN2, respectively, and are adjusted to reduce the stage's voltage offset error.
Typically, the trim approach shown in FIG. 1a is accurate at only one bias condition, and degrades with input common-mode changes (especially in rail-to-rail amplifiers). The tracking of the trim with temperature change is adjusted for temperature by the designer or test engineer, but the temperature trim is not tied to any physical process, but rather must be determined empirically.
Another Vos trim approach involves inserting degeneration resistors into the input pairs' source circuits; two possible schemes are shown in FIGS. 1b and 1c. In FIG. 1b, the amount of current through the resistors is varied by varying their resistance values, to yield a desired offset change at one operating point. In FIG. 1c, tail current is divided between two current sources, and offset trim is varied via trim currents added or subtracted from the tail currents. Unfortunately, this approach can create an undesirable imbalance between the two sides of the input pair. In addition, both of these schemes reduce input stage gain and common-mode input range.